? semiconductor components industries, llc, 2000 may, 2000 rev. 9 1 publication order number: mc74hc244a/d
highperformance silicongate cmos the mc74hc244a is identical in pinout to the ls244. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this octal noninverting buffer/line driver/line receiver is designed to be used with 3state memory address drivers, clock drivers, and other busoriented systems. the device has noninverting outputs and two activelow output enables. the hc244a is similar in function to the hc240a. ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 136 fets or 34 equivalent gates logic diagram data inputs a1 a2 a3 a4 b1 b2 b3 b4 17 15 13 11 8 6 4 218 16 14 12 9 7 5 3 yb4 yb3 yb2 yb1 ya4 ya3 ya2 ya1 noninverting outputs pin 20 = v cc pin 10 = gnd output enables enable a enable b 1 19 function table inputs outputs enable a, enable b a, b ya, yb lll lhh hxz z = high impedance http://onsemi.com marking diagrams 1 20 a = assembly location wl = wafer lot yy = year ww = work week soic wide20 dw suffix case 751d hc244a awlyyww pdip20 n suffix case 738 1 20 mc74hc244an awlyyww tssop20 dt suffix case 948e 1 20 1 20 1 20 device package shipping ordering information mc74hc244an pdip20 1440 / box mc74hc244adw soicwide 38 / rail mc74hc244adwr2 soicwide 1000 / reel mc74hc244adt tssop20 75 / rail mc74hc244adtr2 tssop20 2500 / reel hc 244a alyw 1 20 pin assignment a3 a2 yb4 a1 enable a gnd yb1 a4 yb2 yb3 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 ya2 b4 ya1 enable b v cc b1 ya4 b2 ya3 b3
mc74hc244a http://onsemi.com 2 ??????????????????????? ??????????????????????? maximum ratings* ???? ???? symbol ?????????????? ?????????????? parameter ????? ????? value ??? ??? unit ???? ???? v cc ?????????????? ?????????????? dc supply voltage (referenced to gnd) ????? ????? 0.5 to + 7.0 ??? ??? v ???? ???? v in ?????????????? ?????????????? dc input voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? v out ?????????????? ?????????????? dc output voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? i in ?????????????? ?????????????? dc input current, per pin ????? ????? 20 ??? ??? ma ???? ???? i out ?????????????? ?????????????? dc output current, per pin ????? ????? 35 ??? ??? ma ???? ???? i cc ?????????????? ?????????????? dc supply current, v cc and gnd pins ????? ????? 75 ??? ??? ma ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, plastic dip2 soic package2 tssop package2 ????? ? ??? ? ????? 750 500 450 ??? ? ? ? ??? mw ???? ???? t stg ?????????????? ?????????????? storage temperature ????? ????? 65 to + 150 ??? ??? c ???? ? ?? ? ???? t l ?????????????? ? ???????????? ? ?????????????? lead temperature, 1 mm from case for 10 seconds (plastic dip, soic, ssop or tssop package) ????? ? ??? ? ????? 260 ??? ? ? ? ??? c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c soic package: 7 mw/ c from 65 to 125 c tssop package: 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? symbol ??????????????? ??????????????? parameter ??? ??? min ?? ?? max ??? ??? unit ???? ???? v cc ??????????????? ??????????????? dc supply voltage (referenced to gnd) ??? ??? 2.0 ?? ?? 6.0 ??? ??? v ???? ???? v in , v out ??????????????? ??????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? 0 ?? ?? v cc ??? ??? v ???? ???? t a ??????????????? ??????????????? operating temperature, all package types ??? ??? 55 ?? ?? + 125 ??? ??? c ???? ? ?? ? ???? t r , t f ??????????????? ? ????????????? ? ??????????????? input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v ??? ? ? ? ??? 0 0 0 ?? ?? ?? 1000 500 400 ??? ? ? ? ??? ns dc electrical characteristics (voltages referenced to gnd) ???? ???? ????????? ????????? ????????? ????????? ???? ???? ????????? ????????? guaranteed limit ??? ??? ???? ? ?? ? ???? symbol ????????? ? ??????? ? ????????? parameter ????????? ? ??????? ? ????????? test conditions ???? ? ?? ? ???? v cc v ???? ? ?? ? ???? 55 to 25 c ??? ? ? ? ??? 85 c ???? ? ?? ? ???? 125 c ??? ? ? ? ??? unit ???? ? ?? ? ? ?? ? ???? v ih ????????? ? ??????? ? ? ??????? ? ????????? minimum highlevel input voltage ????????? ? ??????? ? ? ??????? ? ????????? v out = v cc 0.1 v |i out | 20 m a ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 1.5 2.1 3.15 4.2 ??? ? ? ? ? ? ? ??? 1.5 2.1 3.15 4.2 ???? ? ?? ? ? ?? ? ???? 1.5 2.1 3.15 4.2 ??? ? ? ? ? ? ? ??? v ???? ? ?? ? ? ?? ? ???? v il ????????? ? ??????? ? ? ??????? ? ????????? maximum lowlevel input voltage ????????? ? ??????? ? ? ??????? ? ????????? v out = 0.1 v |i out | 20 m a ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 0.5 0.9 1.35 1.8 ??? ? ? ? ? ? ? ??? 0.5 0.9 1.35 1.8 ???? ? ?? ? ? ?? ? ???? 0.5 0.9 1.35 1.8 ??? ? ? ? ? ? ? ??? v ???? ? ?? ? ???? v oh ????????? ? ??????? ? ????????? minimum highlevel output voltage ????????? ? ??????? ? ????????? v in = v ih |i out | 20 m a ???? ? ?? ? ???? 2.0 4.5 6.0 ???? ? ?? ? ???? 1.9 4.4 5.9 ??? ? ? ? ??? 1.9 4.4 5.9 ???? ? ?? ? ???? 1.9 4.4 5.9 ??? ? ? ? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v ih |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma ???? ? ?? ? ???? 3.0 4.5 6.0 ???? ? ?? ? ???? 2.48 3.98 5.48 ??? ? ? ? ??? 2.34 3.84 5.34 ???? ? ?? ? ???? 2.2 3.7 5.2 ??? ? ? ? ??? ???? ? ?? ? ???? v ol ????????? ? ??????? ? ????????? maximum lowlevel output voltage ????????? ? ??????? ? ????????? v in = v il |i out | 20 m a ???? ? ?? ? ???? 2.0 4.5 6.0 ???? ? ?? ? ???? 0.1 0.1 0.1 ??? ? ? ? ??? 0.1 0.1 0.1 ???? ? ?? ? ???? 0.1 0.1 0.1 ??? ? ? ? ??? v ???? ? ?? ? ???? ????????? ? ??????? ? ????????? ????????? ? ??????? ? ????????? v in = v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma ???? ? ?? ? ???? 3.0 4.5 6.0 ???? ? ?? ? ???? 0.26 0.26 0.26 ??? ? ? ? ??? 0.33 0.33 0.33 ???? ? ?? ? ???? 0.4 0.4 0.4 ??? ? ? ? ??? this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc244a http://onsemi.com 3 dc electrical characteristics (voltages referenced to gnd) ??? ??? ????????? ????????? guaranteed limit ???? ???? ????????? ????????? ????????? ????????? ???? ???? ??? ??? unit ???? ???? 125 c ??? ??? 85 c ???? ???? 55 to 25 c ???? ???? v cc v ????????? ????????? test conditions ????????? ????????? parameter ???? ???? symbol ???? ? ?? ? ???? i in ????????? ? ??????? ? ????????? maximum input leakage current ????????? ? ??????? ? ????????? v in = v cc or gnd ???? ? ?? ? ???? 6.0 ???? ? ?? ? ???? 0.1 ??? ? ? ? ??? 1.0 ???? ? ?? ? ???? 1.0 ??? ? ? ? ??? m a ???? ? ?? ? ???? i oz ????????? ? ??????? ? ????????? maximum threestate leakage current ????????? ? ??????? ? ????????? output in highimpedance state v in = v il or v ih v out = v cc or gnd ???? ? ?? ? ???? 6.0 ???? ? ?? ? ???? 0.5 ??? ? ? ? ??? 5.0 ???? ? ?? ? ???? 10 ??? ? ? ? ??? m a ???? ? ?? ? ???? i cc ????????? ? ??????? ? ????????? maximum quiescent supply current (per package) ????????? ? ??????? ? ????????? v in = v cc or gnd i out = 0 m a ???? ? ?? ? ???? 6.0 ???? ? ?? ? ???? 4.0 ??? ? ? ? ??? 40 ???? ? ?? ? ???? 160 ??? ? ? ? ??? m a note: information on typical parametric values and high frequency or heavy load considerations can be f ound in chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) ????? ????? ???????????????? ???????????????? ???? ???? ????????? ????????? guaranteed limit ??? ??? ????? ????? symbol ???????????????? ???????????????? parameter ???? ???? v cc v ???? ???? 55 to 25 c ??? ??? 85 c ???? ???? 125 c ??? ??? unit ????? ? ??? ? ? ??? ? ????? t plh , t phl ???????????????? ? ?????????????? ? ? ?????????????? ? ???????????????? maximum propagation delay, a to ya or b to yb (figures 1 and 3) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 96 50 18 15 ??? ? ? ? ? ? ? ??? 115 60 23 20 ???? ? ?? ? ? ?? ? ???? 135 70 27 23 ??? ? ? ? ? ? ? ??? ns ????? ? ??? ? ? ??? ? ????? t plz , t phz ???????????????? ? ?????????????? ? ? ?????????????? ? ???????????????? maximum propagation delay, output enable to ya or yb (figures 2 and 4) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 110 60 22 19 ??? ? ? ? ? ? ? ??? 140 70 28 24 ???? ? ?? ? ? ?? ? ???? 165 80 33 28 ??? ? ? ? ? ? ? ??? ns ????? ? ??? ? ? ??? ? ????? t pzl , t pzh ???????????????? ? ?????????????? ? ? ?????????????? ? ???????????????? maximum propagation delay, output enable to ya or yb (figures 2 and 4) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 110 60 22 19 ??? ? ? ? ? ? ? ??? 140 70 28 24 ???? ? ?? ? ? ?? ? ???? 165 80 33 28 ??? ? ? ? ? ? ? ??? ns ????? ? ??? ? ? ??? ? ????? t tlh , t thl ???????????????? ? ?????????????? ? ? ?????????????? ? ???????????????? maximum output transition time, any output (figures 1 and 3) ???? ? ?? ? ? ?? ? ???? 2.0 3.0 4.5 6.0 ???? ? ?? ? ? ?? ? ???? 60 23 12 10 ??? ? ? ? ? ? ? ??? 75 27 15 13 ???? ? ?? ? ? ?? ? ???? 90 32 18 15 ??? ? ? ? ? ? ? ??? ns ????? ????? c in ???????????????? ???????????????? maximum input capacitance ???? ???? e ???? ???? 10 ??? ??? 10 ???? ???? 10 ??? ??? pf ????? ? ??? ? ????? c out ???????????????? ? ?????????????? ? ???????????????? maximum threestate output capacitance (output in highimpedance state) ???? ? ?? ? ???? e ???? ? ?? ? ???? 15 ??? ? ? ? ??? 15 ???? ? ?? ? ???? 15 ??? ? ? ? ??? pf note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d). typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (per buffer)* 34 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor highspeed cmos data book (dl129/d).
mc74hc244a http://onsemi.com 4 switching waveforms figure 1. figure 2. v cc gnd t f t r data input a or b output ya or yb 10% 50% 90% 10% 50% 90% t tlh t plh t phl t thl enable a or b output y output y 50% 50% 50% 90% 10% t pzl t plz t pzh t phz v cc gnd high impedance v ol v oh high impedance test circuits *includes all probe and jig capacitance c l * test point device under test output figure 3. test circuit *includes all probe and jig capacitance c l * test point device under test output figure 4. test circuit connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k w pin descriptions inputs a1, a2, a3, a4, b1, b2, b3, b4 (pins 2, 4, 6, 8, 11, 13, 15, 17) data input pins. data on these pins appear in noninverted form on the corresponding y outputs, when the outputs are enabled. controls enable a, enable b (pins 1, 19) output enables (activelow). when a low level is applied to these pins, the outputs are enabled and the devices function as noninverting buffers. when a high level is applied, the outputs assume the high impedance state. outputs ya1, ya2, ya3, ya4, yb1, yb2, yb3, yb4 (pins 18, 16, 14, 12, 9, 7, 5, 3) device outputs. depending upon the state of the outputenable pins, these outputs are either noninverting outputs or highimpedance outputs.
mc74hc244a http://onsemi.com 5 logic detail data input a or b enable a or enable b to three other a or b inverters one of 8 inverters ya or yb v cc
mc74hc244a http://onsemi.com 6 package dimensions so20 dw suffix case 751d05 issue f pdip20 n suffix plastic dip package case 73803 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc74hc244a http://onsemi.com 7 package dimensions tssop20 dt suffix case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane w. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 s u 0.15 (0.006) t
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